A field programmable gate array (FPGA) is a type of integrated circuit consisting of an array of programmable logic blocks (PLBS) interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells or boundary ports is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application
The present inventors have recently developed methods of built-in self-testing the array of PLBs in FPGAs at the device, board and system levels. These methods are set out in detail in U.S. Pat. No. 5,998,907 and U.S. Pat. No. 6,003,150. The fill disclosures in these patent applications are incorporated herein by reference.
In each of these prior methods, the reprogrammability of an FPGA is exploited so that the FPGA is configured exclusively with built-in self-test (BIST) logic during testing and subsequently reconfigured to its normal operating configuration. In this way, testability at every level is achieved without overhead. In other words, the BIST logic simply "disappears" when the FPGA is reconfigured for its normal system function. The only cost or additional hardware required for these testing methods is memory for storing the BIST configuration data required for testing and the normal operating configuration required for subsequently reconfiguring the FPGA. This additional memory, however, may be made a part of the test machine environment, e.g., automatic testing equipment, a central processing unit or a maintenance processor, thereby not involving FPGA resources.
In addition to testing the array of PLBs, complete FPGA testing further requires the testing of the programmable routing network. Heretofore, testing of the programmable routing network was accomplished utilizing externally applied test vectors. While the use of test vectors is effective in testing of the programmable routing network, these tests are applicable only for specific device-level manufacturing tests. Accordingly, a need is identified for testing the entire programmable routing network at the device, circuit board and system levels.